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Lead Formal Verification Engineer

Join Pure Silicon, a cutting-edge team reshaping the world of semiconductor design through Formal Verification. If you're passionate about pushing the boundaries of what formal verification can achieve and want to shape the future of chip design verification, this role is for you.

About the Role :

As a Lead Formal Verification Engineer, you will architect, implement, and drive formal verification methodologies across complex IP, Subsystem, and SoC designs. You will take ownership of customer interactions, define comprehensive verification plans, and apply advanced abstraction techniques to resolve deep convergence challenges. You will operate independently, providing leadership and technical direction while mentoring engineers to foster a robust formal verification culture across the organization.

Work location :

For this role is Budapest (Hungary); or SF Bay Area (USA); or Hybrid for suitable well qualified and experienced individual.

Responsibilities :

Provide technical leadership in Formal Verification, defining methodologies, strategies, and execution plans.
Collaborate closely with architecture and design teams to create formal-driven specifications that guarantee correctness.
Drive the adoption of AI-assisted verification methodologies to improve team productivity while preserving the strict rigor, traceability, and quality standards required for silicon signoff.
Develop, implement, and optimize scalable, reusable Formal Verification environments to improve efficiency and reliability across projects.
Define verification scope, apply abstraction models, and close coverage using advanced Formal Verification techniques across IP, Subsystem, and SoC levels.
Lead the evaluation and integration of EDA tools (e.g., JasperGold, VC-Formal, Questa-Formal), recommending best-in-class solutions to maximize verification efficiency.
Mentor and train engineers, fostering a strong Formal Verification cultureand establishing rigorous validation review processes for AI-generated assets before deployment.
Integrate hybrid verification approaches, bridging formal methods with simulation-based environments for enhanced coverage.

Qualifications :

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in RTL Design/Verification, with at least 3 years specializing in Formal Verification.
Strong proficiency in SystemVerilog Assertions (SVA) and core formal methodologies.
Hands-on expertise with industry-standard formal tools (JasperGold, VC-Formal, or Questa-Formal).
Solid understanding of complexity reduction, abstraction techniques, and Formal Verification sign-off (including ProofCore and cone of influence analysis).
Experience leveraging AI-powered development tools (e.g., GitHub Copilot, Claude, GPT, Gemini) to accelerate property generation, RTL analysis, debug, and documentation.
Experience verifying DSP, CPU, GPU, or hardware accelerators using advanced formal techniques.
Familiarity with clock domain crossing (CDC), low-power design verification, and IP-XACT-based register verification.
Outstanding communication, collaboration, and customer-facing skills.
Experience with scripting languages (Python, Perl, Tcl) to build automated specification-to-design flows.

Pure Silicon Solutions (PSS) is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

At PSS, we offer a total compensation package with a base salary, bonus, and stock options. Salary will be commensurate with job-related skills, experience and work location.

Innovative Work

Shape the future of Formal Verification by tackling groundbreaking projects

Dynamic Team

Work with a close-knit team of passionate experts in a supportive and collaborative environment

Flexibility

Enjoy a work culture that values balance, offering hybrid work options and an adaptable
approach to team needs

Lead UVM Verification Engineer

Pure Siliconis growing, and we’re looking for a Lead UVM Verification Engineer to join our team. If you're passionate about building world-class verification environments and driving complex SoC programs to success, this role is for you.

About the Role :

As a Lead UVM Verification Engineer, you will architect, implement, and drive UVM-based verification for complex IP and SoC designs. You will collaborate directly with hardware, firmware, and DV teams to ensure functional correctness, performance, and reliability while playing a key leadership role in methodology, execution, and team development. This position requires responsibility for tracking verification progress against goals and schedule, identifying gaps, and adapting plans to ensure timely and complete closure.

Work location :

For this role is Budapest (Hungary); or SF Bay Area (USA); or Hybrid for suitable well qualified and experienced individual.

Responsibilities :

Architect and implement UVM-based testbenches for complex SoCs and IP blocks.
Define, execute, and maintain verification plans aligned to design specs and program milestones.
Develop reusable UVCs, scoreboards, and reference models with a strong emphasis on modularity and maintainability.
Drive simulation-based verification using constrained-random, directed tests, and assertions.
Collaborate closely with design, firmware, and DV teams to triage issues and close functional/code coverage.
Drive the adoption of AI-assisted verification methodologies to improve team productivity while preserving the strict rigor, traceability, and quality standards required for silicon signoff.
Integrate, analyze, and act on functional and code coverage metrics.
Lead HW/SW co-verification, including firmware interactions and driver-level testing.
Track verification progress against goals and time budget; adjust plans as needed to ensure alignment.
Mentor junior engineers, contribute to verification methodology improvements, and establish best practices for the responsible use and validation of AI-generated content within the verification flow.

Qualifications :

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or a related field.
8+ years of experience in simulation-based hardware verification.
Strong expertise in SystemVerilog and UVM methodology.
Proven experience with SoC-level verification and HW/SW co-verification.
Experience leveraging AI-powered development tools (e.g., GitHub Copilot, Claude, Gemini) to accelerate testbench generation, debug, scripting, and coverage closure.
Hands-on experience with common industry protocols (PCIe, Ethernet, AMBA AHB/AXI).
Excellent debugging skills using waveforms, assertions, and simulation logs.
Familiarity with coverage-driven verification and regression infrastructure.
Strong communication and collaboration skills.
Experience with scripting languages (Perl, TCL, Python, etc.).

Innovative Work

Shape the future of Formal Verification by tackling groundbreaking projects

Dynamic Team

Work with a close-knit team of passionate experts in a supportive and collaborative environment

Flexibility

Enjoy a work culture that values balance, offering hybrid work options and an adaptable
approach to team needs

At PSS, we offer a total compensation package with a base salary, bonus, and stock options. Salary will be commensurate with job-related skills, experience and work location.